DocumentCode
2636567
Title
Bit-level systolic array for FIR filter using AND-based bit-serial multiplier
Author
Lee, Jae-Jin ; Song, Gi-Yong
Author_Institution
Sch. of Electr. & Comput. Eng., Chungbuk Nat. Univ., Cheongju Chungbuk, South Korea
Volume
1
fYear
2003
fDate
15-17 Oct. 2003
Firstpage
87
Abstract
The paper proposes a bit-level systolic array for FIR digital filter with an AND-based bit-serial pipelined multiplier inside. Compared to the conventional systolic array for FIR filter based on word-level data flow, the bit-level systolic array for FIR filter is very compact in that it needs only two 1-bit I/O ports in addition to reduced area requirement without time penalty on the output sequence.
Keywords
FIR filters; digital filters; multiplying circuits; pipeline arithmetic; systolic arrays; AND-based bit-serial multiplier; FIR filter; bit-level systolic array; digital filter; pipelined multiplier; word-level data flow; Arithmetic; Communications technology; Digital filters; Digital signal processing; Finite impulse response filter; Integrated circuit interconnections; Parallel processing; Pipelines; Signal processing algorithms; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2003. Conference on Convergent Technologies for the Asia-Pacific Region
Print_ISBN
0-7803-8162-9
Type
conf
DOI
10.1109/TENCON.2003.1273235
Filename
1273235
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