An efficient hardware implementation of DWT and IDWT

Real-time applications of discrete wavelet transform (DWT), like video and audio compression, necessitate fast computation of DWT. Full-custom VLSI devices have been used for fast, though expensive, implementations of DWT. Field-programmable gate array (FPGA) architectures offer economical but area-constrained implementation of DWT. The paper proposes an efficient FPGA architecture for DWT as well as inverse DWT (IDWT). Use of distributed arithmetic allows us to do without area-consuming multipliers in the present realization. The proposed architecture is modular and allows extension to any precision without much effect on the clock frequency. Simulation results have established that the proposed fast implementation scheme can produce high-quality reconstructed signals.