Title :
Asynchronous self-timed circuit synthesis with timing constraints
Author :
Hung, Andy ; Meng, T.H.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
Incorporating timing information into asynchronous self-timed circuit synthesis can improve circuit performance and simplify circuit hardware. Algorithms are presented that use timing constraints to reduce dependencies of circuit behavior on signal transitions. The resulting asynchronous self-timed circuit is not delay-insensitive in general, but preserves the desirable feature of a hazard-free design under the given timing information
Keywords :
asynchronous sequential logic; graph theory; logic design; asynchronous self-timed circuit; circuit synthesis; hazard-free design; timing constraints; timing information; Algorithm design and analysis; Circuit optimization; Circuit synthesis; Clocks; Delay; Hardware; Laboratories; Signal analysis; Timing;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112316
