Synthesizing DSP architectures from behavioral specifications: a formal approach

A formal behavioral synthesis framework is introduced for specification, simulation, and synthesis of digital signal processing (DSP) algorithms. The given algorithm is represented using a newly developed language called the algorithm specification language (ASL). The components and connectivity of the synthesized architecture can be represented in three different forms: a language called the realization specification language (RSL), schematic captures, and PROLOG. PROLOG is used as a user interface language between the user subsystem and the synthesis subsystem. Algorithms of linear time complexity are introduced for transferring between different representations