Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level channel bit error rate requirement for high bandwidth systems. The parameters which influence the channel and it´s interconnect environment are primarily governed by signal integrity and power integrity requirements. In this paper, system level robustness analysis of high speed serial links is demonstrated with external environment considerations taken into account. A strong correlation between measured and simulated results is shown. A generic methodology for high speed serial links is presented with complete analysis of package, board, termination, signal quality inrush Droop/Drop (SQiDD), decoupling network etc.