Title :
Design of a Highly Dependable Beamforming Chip
Author :
Zhang, X. ; Kerkhoff, H.G.
Author_Institution :
Testable Design & Test of Integrated Syst. Group, Univ. of Twente, Enschede, Netherlands
Abstract :
As CMOS process technology advances towards 32 nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural IP (IIP) and supporting software and hardware have been designed and included as part of the dependability infrastructure of the chip. This IIP can periodically verify the correctness of the tile processors and coordinate the run-time mapping reconfiguration software to isolate the faulty tiles at run time and assign spare processors for the open DSP tasks. Dependability graphs show a significant improvement of the application chip incorporating the design-for-dependability hardware and software.
Keywords :
CMOS digital integrated circuits; digital signal processing chips; integrated circuit reliability; reconfigurable architectures; system-on-chip; CMOS process; IEC standard 62347; SoC complexity; dependability graphs; design-for-dependability hardware; design-for-dependability software; functional dependability analysis; highly dependable beamforming chip; reconfigurable Xentium tile processors; run-time mapping reconfiguration software; size 32 nm; Application software; Array signal processing; CMOS process; CMOS technology; Digital signal processing chips; Hardware; IEC standards; Runtime; Software design; Tiles; SoC; beamforming; dependability; design-for-dependability; reconfigurable tile processor;
Conference_Titel :
Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on
Conference_Location :
Patras
Print_ISBN :
978-0-7695-3782-5
DOI :
10.1109/DSD.2009.152
