Synthesis of asynchronous state machines using a local clock

A novel, correct design methodology for asynchronous state-machine controllers is presented. The goal of this work is a design style as close to a synchronous one as possible, but with the advantages of an asynchronous method. The implementations realize asynchronous state-machine specifications using standard combinational logic, flow latches as storage elements, and a locally-generated clocking signal that pulses whenever there is a change in state. This design style allows multiple input changes which can arrive at arbitrary times. The implementations use a minimal or near-minimal number of states. It also allows arbitrary state encoding and flexibility in logic minimization and gate-level realization, so it can take advantage of systematic CAD optimization techniques