DocumentCode
2637197
Title
Survey of Test Data Compression Technique Emphasizing Code Based Schemes
Author
Mehta, Usha ; Dasgupta, K.S. ; Devashrayee, N.M.
Author_Institution
Nirma Univ., Ahmedabad, India
fYear
2009
fDate
27-29 Aug. 2009
Firstpage
617
Lastpage
620
Abstract
As a result of the emergence of new fabrication technologies and design complexities, standard stuck-at scan tests are no longer sufficient. The number of tests and corresponding data volume increase with each new fabrication process technology. The demand goes to well beyond 100X tester cycle reduction considering new fault models. The test data compression has been an emerging need of VLSI field and the hot topic of research for last decade. Still there is a great need and scope for further reduction in test data volume. This reduction must be lossless for input side test data. This paper summarizes the different methods based on coding theory applied for lossless compression of the input side test data. It covers starting with simple code based methods to combine/hybrid methods. The basic goal here is to prepare survey on current methodologies applied for test data compression and prepare a platform for further development in this avenue.
Keywords
VLSI; data compression; fault diagnosis; 100X tester cycle reduction; VLSI field; code-based schemes; coding theory; data compression technique; design complexity; fault models; standard stuck-at scan tests; Automatic test pattern generation; Bandwidth; Circuit faults; Circuit testing; Decoding; Fabrication; Hardware; Space technology; System testing; Test data compression; Automatic Test Equipment; Code Based Data Compression; FDR code; Huffman Code; Test Data Compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on
Conference_Location
Patras
Print_ISBN
978-0-7695-3782-5
Type
conf
DOI
10.1109/DSD.2009.134
Filename
5350179
Link To Document