Title :
A 10 Gb/s low-power 4:1 multiplexer in 0.18 μm CMOS
Author :
Sun, Xiang ; Feng, Jun
Author_Institution :
Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China
Abstract :
To reduce the power consumption, a 4:1 multiplexer using the CMOS logic is presented for high-speed operation. The proposed circuit adopts tree-type and half-rate structure. The CMOS logic, such as the dynamic CMOS and pseudo-static CMOS logic, is renewed in this design. The designed circuit is realized in a standard 0.18 μm CMOS process and uses 1.8 V supply voltage. The post simulated result shows that the fully integrated MUX operates well up to 10 Gb/s. The simulated eye opening is 200 mVpp on an external 50 Ohm load. The power consumption of the MUX is 53.3 mW at 10 Gb/s. The overall chip has a size of 0.575×0.475 mm2 and the core size is 0.18×0.12 mm2.
Keywords :
CMOS logic circuits; multiplexing equipment; power consumption; half-rate structure; high-speed operation; low-power multiplexer; power 53.3 mW; power consumption; pseudostatic CMOS logic; size 0.18 mum; tree-type structure; voltage 200 mV; CMOS integrated circuits; Clocks; Integrated circuit modeling; Inverters; Latches; Multiplexing; Power demand;
Conference_Titel :
Signals Systems and Electronics (ISSSE), 2010 International Symposium on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-6352-7
DOI :
10.1109/ISSSE.2010.5607122