Generation of finite state machines from parallel program graphs in DIADES

Author

Perkowski, Marek A. ; Liu, Jiuling

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

1139

Abstract

A method is presented for describing parallel program graphs in a high-level synthesis system. Such descriptions are, in general, similar to Karp and Miller parallel program schemata and are more general than Petri nets. It is shown how these graphs are converted to sequential program schemata and then to finite state machines (FSMs) in such a way that the number of states is minimized. The entire FSM synthesizer for control unit synthesis in a comprehensive design automation system is presented and illustrated with a complete example. The synthesizer makes use of inputs and state minimization, state assignment, and logic minimization of FSMs

Keywords

finite automata; graph theory; logic CAD; minimisation of switching nets; parallel programming; state assignment; CAD; DIADES; design automation system; finite state machines; high-level synthesis system; logic minimization; parallel program graphs; sequential program schemata; state assignment; state minimization; Automata; Automatic control; Control system synthesis; Control systems; Design automation; Digital systems; Hardware; Logic; Minimization; Synthesizers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112320

Filename

112320