DocumentCode
2637275
Title
CPLD-oriented Synthesis of Finite State Machines
Author
Czerwinski, Robert ; Kania, Dariusz
Author_Institution
Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
fYear
2009
fDate
27-29 Aug. 2009
Firstpage
521
Lastpage
528
Abstract
The purpose of the paper is to present a new approach to FSM synthesis for PAL-based CPLDs. The proposed approach consists of the original method of the state assignment and PAL-oriented multi-level optimization. The aim of the proposed state assignment method is to minimize the number of the PAL-based macrocells by fitting the FSM to the structure of the CPLD as good as possible. The essence of PAL-oriented multi-level optimization is to search for multi-output implicants that can be shared by several functions. Results of experiments prove that the proposed algorithm leads to significant reduction of chip area in relation to the previously published methods and vendor-tools.
Keywords
finite state machines; programmable logic arrays; state assignment; CPLD; FSM; PAL-oriented multilevel optimization; finite state machine synthesis; state assignment method; Automata; Automatic testing; Design methodology; Digital systems; Energy consumption; Field programmable gate arrays; Logic arrays; Macrocell networks; Optimization methods; Paper technology; CPLD; FSM; logic optimization; logic synthesis; state assignment;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on
Conference_Location
Patras
Print_ISBN
978-0-7695-3782-5
Type
conf
DOI
10.1109/DSD.2009.173
Filename
5350183
Link To Document