Algorithm and VLSI architecture of a parallel arithmetic entropy coder for parallel H.264 video encoders

This paper proposes the algorithm and its hardware architecture of a new CABAC-based parallel arithmetic entropy coder for on-chip large-scale parallel H.264 video coders. The proposed entropy coder partitions syntax elements into three independent groups according to their semantic dependencies, and processes them in three parallel threads, each of which is implemented as a fully pipelined hardware accelerator driving by Syntax Element Instructions. To preserve decodability, each thread of the proposed entropy coder deals with the syntax elements in the way of CABAC. This orthogonality allows the previous symbol-level parallel techniques to be applied in each of its threads to further improve the throughput. However, this feature also constrains the partitioning of the syntax elements and thus the obtained speedups. Simulation and physical implementation results show that, the proposed coder can double its throughput at the expense of about 60% hardware transistors compared to CABAC while keeping the advantage of arithmetic coding against the other methods.