A new capacitor-ratio-independent algorithmic analog-to-digital converter

Author

Wu, Chung-Yu ; Chin, Shu-Yuan ; Chang, Shin-Shi

Author_Institution

Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan

fYear

1990

fDate

1-3 May 1990

Firstpage

2228

Abstract

The design of a capacitor-ratio-independent algorithmic analog-to-digital converter (ADC) that is inherently insensitive to both capacitor ratio and amplifier offset voltage due to the use of switched-capacitor techniques is described. It can also be realized in a small chip area using p-well CMOS technology. This A/D converter completes n-bit conversion in 2n clock cycles, which is faster than previously reported converters. It is shown that the single-ended-output type of the ADC can achieve a 12-b resolution at a sampling rate of 42 kHz. SPICE simulations have been performed to verify the operation of this A/D converter

Keywords

CMOS integrated circuits; analogue-digital conversion; switched capacitor networks; 42 kHz; A/D converter; SPICE simulations; algorithmic ADC; amplifier offset voltage; capacitor-ratio-independent; monolithic IC; p-well CMOS technology; single-ended-output type; switched-capacitor techniques; Algorithm design and analysis; Analog-digital conversion; Capacitors; Circuits; Clocks; Design engineering; Operational amplifiers; SPICE; Sampling methods; Switching converters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112321

Filename

112321