A 2.5-Gb/s CMOS Clock And Data Recovery Circuit With A 1/4 Rate Linear Phase Detector And Lock Detector

Author

Alavi, S.M. ; Shoaei, O.

Author_Institution

Tehran Univ.

fYear

2006

fDate

22-24 June 2006

Firstpage

175

Lastpage

178

Abstract

An OC-48 phase-lock clock and data recovery (CDR) circuit is proposed, supported by system and circuit (CMOS 0.35mum) level simulation for SONET (2.488/2.688-Gb/s) transceiver applications. The CDR circuit exploits quarter rate linear phase detector. A novel quadrature ring oscillator using new active inductor is also introduced that operates at quarter rate of the original clock. Also for frequency locking this paper uses a lock detector. Making use of the frac14 linear phase detector (PD) facilitates the design of voltage controlled oscillator (VCO) and eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recovered data

Keywords

CMOS integrated circuits; SONET; clocks; frequency locked loops; inductors; phase detectors; transceivers; voltage-controlled oscillators; 0.35 micron; 2.488 to 2.688 Gbit/s; CMOS technology; SONET transceiver; active inductor; circuit level simulation; clock and data recovery circuit; frequency locking; lock detector; quadrature ring oscillator; quarter rate linear phase detector; voltage controlled oscillator; Active inductors; Circuit simulation; Clocks; Detectors; Frequency; Phase detection; Ring oscillators; SONET; Transceivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706562

Filename

1706562