A 3.2 Gbit/s CML Transmitter With 20:1 Multiplexer In 0.18 CMOS Technology

Author

Hsiao, C.H. ; Kao, M.S. ; Jen, C.H. ; Hsu, Y.H. ; Yang, P.L. ; Chiu, C.T. ; Wu, J.M. ; Hsu, S.H. ; Hsu, Y.S.

Author_Institution

National Tsing Hua Univ., Hsinchu

fYear

2006

fDate

22-24 June 2006

Firstpage

179

Lastpage

183

Abstract

In this paper, a 3.2Gb/s CML transmitter with 20:1 multiplexer was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers or switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serialization with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer could provide 250mV output voltage swing up to 10Gb/s. The overall chip size is 650mumtimes950mum with power consumption of 104 mW at 3.2Gb/s

Keywords

CMOS integrated circuits; buffer circuits; current-mode logic; multiplexing equipment; phase locked loops; transmitters; 0.18 micron; 104 mW; 250 mV; 3.2 Gbit/s; 650 micron; 950 micron; CML transmitter; CMOS technology; differential circuit; double phase source coupled logic; high speed CML output buffer; high speed network; low-power phase locked loop; multiplexer; on chip dual phase clocks; CMOS technology; Circuit noise; Coupling circuits; Frequency; High-speed networks; Logic circuits; Multiplexing; Noise reduction; Switches; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706563

Filename

1706563