Title :
Syndrome-based functional delay fault location in linear digital data-flow graphs
Author :
Chatterjee, Abhijit ; D´Abreu, Manuel A.
Author_Institution :
GE Corp. Res. & Dev., Schenectady, NY, USA
Abstract :
A novel approach to fault location in linear digital data flow graphs is presented. The fault location scheme is simple and depends on the linearity property of these data flow graphs. Identification and replacement of the failed component allows operation of the circuit at the desired clock speed. It is shown how timing problems identified during speed testing of a class of circuits widely used in digital signal processing and control can be isolated to individual or sets of circuit components
Keywords :
fault location; graph theory; sequential circuits; clock speed; digital signal processing; failed component; linear digital data-flow graphs; speed testing; syndrome based functional delay fault location; timing problems; Adders; Circuit faults; Circuit testing; Clocks; Delay; Fault diagnosis; Fault location; Integrated circuit interconnections; Packaging; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139883
