A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

Author

Moradi, F. ; Peiravi, A. ; Mahmoodi, H.

Author_Institution

Islamic Azad Univ.

fYear

2006

fDate

22-24 June 2006

Firstpage

210

Lastpage

213

Abstract

As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results obtained using the 70nm Berkeley predictive models, our proposed circuit increases the noise immunity by least 2times compared to previous circuits

Keywords

CMOS logic circuits; integrated circuit noise; leakage currents; logic design; 70 nm; Berkeley predictive models; domino logic circuit; footer transistor; leakage tolerance; noise immunity; ultra deep submicron CMOS; CMOS logic circuits; CMOS process; Circuit noise; Circuit simulation; Circuit synthesis; Leakage current; Logic circuits; Manufacturing processes; Predictive models; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706570

Filename

1706570