Title :
Signal processing for low SNR digital communications
Author :
Marino, Claudio S. ; Chau, Paul M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
Advancements in VLSI technology allow for the digitization of communication systems and the utilization of more sophisticated signal processing algorithms, such as turbo codes for stronger forward error correction (FEC) processing. However, commiserate improvements must also occur in front-end processing for signal acquisition. A new architecture that merges the functionality of front-end and back-end signal processing for more VLSI efficient hardware in low SNR (LSNR) communications environments offering the potential to reduce the overall complexity and cost of the implementation is presented. Simulations show that this architecture is comparable in performance with current implementations.
Keywords :
VLSI; correlation methods; digital communication; digital signal processing chips; forward error correction; noise; satellite computers; signal detection; turbo codes; FEC processing; VLSI technology; back-end signal processing; digital communication systems; forward error correction; front-end processing; implementation complexity reduction; implementation cost reduction; low SNR digital communications; performance; reduced complexity correlation estimator; signal acquisition; signal processing algorithms; simulations; turbo codes; Adaptive signal processing; Digital communication; Digital signal processing; Field programmable gate arrays; Forward error correction; Hardware; Signal processing algorithms; Vehicle dynamics; Very large scale integration; Wireless communication;
Conference_Titel :
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5148-7
DOI :
10.1109/ACSSC.1998.751414
