A Wide Range Clock Management Pll With Full Period Phase-shifting Of The Divided Clock

Author

McDonagh, D. ; Arshak, K.I. ; Abubaker, O.

Author_Institution

Toumaz Technol. Ltd., Abingdon

fYear

2006

fDate

22-24 June 2006

Firstpage

228

Lastpage

233

Abstract

In this paper, a clock management CMOS PLL with full period phase-shifting of the divided clock is presented. The full-period phase-shifting is performed by generating a multitude of unique divided clock signals evenly spaced in time over one period of the divided clock and re-synchronising with the various oscillator output phases. Low swing current mode/differential pair logic has been used in this design. The current controlled oscillator is an interpolating feed-forward differential ring structure with 12 output phases. The typical oscillator tuning range is 85 to 720MHz. The phase noise at 1MHz offset from the oscillator frequency is -106.8dBc. To enable high-rate off-chip clocking, a new LVDS transmitter cell is designed and works over the full frequency range of the oscillator

Keywords

CMOS integrated circuits; VHF oscillators; clocks; current-mode logic; integrated circuit design; phase locked loops; phase noise; phase shifters; 85 to 720 MHz; LVDS transmitter cell; clock management CMOS PLL; clock management PLL; current controlled oscillator; current mode logic; differential pair logic; divided clock signals; feedforward differential ring structure; full period phase-shifting; oscillator output phases; oscillator tuning range; phase locked loop; phase noise; Clocks; Feedforward systems; Frequency; Logic design; Phase locked loops; Phase noise; Ring oscillators; Signal generators; Transmitters; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706574

Filename

1706574