Fault-tolerance in FPGA focusing power reduction or performance enhancement

The purpose of this paper is to present a Fault-Tolerance methodology for FPGA-based designs, focusing power reduction or performance enhancement during on-field operation. The methodology is based on a new performance sensor which predictively detects errors in critical paths, either allowing power-supply voltage (VDD) to be reduced, or clock frequency (fclk) to be raised, driving power reduction or performance increase. The HDL sensor´s functionality is defined by the designer, according to the target circuit configuration in the FPGA structure. The adaptive scheme uses an Automatic Voltage and Frequency Controller (AVFC) to modify fclk and/or VDD, while still guaranteeing safe operation. The built-in sensors identify performance deviations in pre-identified critical paths during circuit operation and along product lifetime, caused by parametric variations and/or aging. The fclk increase is made possible by reducing the pessimistic safety-margins defined by standard simulation tools to account for variability. The sensors delay margins are programmable, so an adequate delay margin can guarantee safe operation. Conversely, the same performance can be achieved with lower VDD. Simulation and experimental results with Virtex 5 and Spartan 6 FPGAs show that significant performance improvements (typically, 30%) can be achieved with this methodology.