Reducing peak power consumption of combinational test sets

Besides fault coverage and application time, another important parameter that must be considered for evaluating the quality of a given set of test vectors (i.e., a test set) is the peak power the circuit dissipates when the vectors are sequentially supplied at the primary input pins. In this paper we address the problem of minimizing the peak power of a given combinational test set. We present an effective, graph-based solution to generate a power-conscious test set that is minimally intrusive with respect to the original one. Besides achieving reduced peak power consumption, our algorithm guarantees the initial fault coverage to be preserved, and the size of the newly generated test set to be kept under strict control. We have applied our technique to test sets generated by a state-of-the-art ATPG tool for all the Iscas´85 combinational benchmark circuits. The results we have obtained are very promising, and indicate the practical applicability of the proposed solution.