F-gate: a device for glitch power minimization

Gate freezing is an innovative technique for glitch power minimization in logic circuits. The method is based on the idea of transforming some selected high-glitching gates into modified devices, called F-gates, that are able to filter out spurious transitions whenever a proper control signal is activated. The availability of an efficient implementation, in terms of performance, of the modified gates is the key in making the technique applicable in practice. We discuss design issues and explore the characteristics of F-gates. From our analysis we can conclude that F-gates can be safely used in practice as glitch filtering elements, and can thus be fruitfully exploited by the gate freezing optimization paradigm.