DocumentCode
2638346
Title
An energy efficient scheduling scheme for signal processing applications
Author
Krishna, Vamsi ; Ranganathan, N. ; Vijaykrishnan, N.
Author_Institution
Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
Volume
2
fYear
1998
fDate
1-4 Nov. 1998
Firstpage
1057
Abstract
We propose a time constrained energy efficient scheduling technique for signal processing applications. Specifically, we propose a scheduling algorithm, (DFMVS), which utilizes the concept of dynamic frequency clocking and multiple voltage scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. This feature of dynamic frequency clocking gives enough slack for multiple voltages to be used for energy minimization. DFMVS has been applied to some DSP benchmarks and the results show an average reduction of 31.6% in energy dissipated as compared to using a uni-frequency clocking scheme with a single supply voltage.
Keywords
clocks; delays; digital signal processing chips; energy conservation; high level synthesis; DFMVS; DSP benchmarks; delay model; dissipated energy reduction; dynamic frequency clocking; energy minimization; functional unit; high level synthesis; multiple voltage scaling; scheduling algorithm; signal processing applications; single frequency clocking; single supply voltage; time constrained energy efficient scheduling; Application software; Clocks; Computer science; Energy efficiency; Frequency; Power engineering and energy; Processor scheduling; Signal processing; Time factors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-5148-7
Type
conf
DOI
10.1109/ACSSC.1998.751424
Filename
751424
Link To Document