An alternative architecture for on-chip global interconnect: segmented bus power modeling

On-chip interconnect power consumption has become an important issue as technology quickly scales down and the industry embraces system-on-a-chip (SOC). The simple bus structure may became a serious bottleneck in reducing the total chip power consumption and increasing performance due to transmission line effects. Alternative interconnect structures should be considered under this circumstances. This paper models the power consumption of both a global data bus and the proposed segmented bus for a commercial chip at the behavioral level. The chip is an integration of a 16-bit DSP and a 32-bit RISC microcontroller. The power measurements of both bus structures at different technology feature size levels are reported for a set of standard signal processing benchmarks.