Implementation Of The Conscience Mechanism For Kohonen´s Neural Network In Cmos 0.18 /spl mu/m Technology

Author

Talaska, Tomasz ; Wojtyna, R. ; Dlugosz, Rafal ; Iniewski, K.

Author_Institution

Technol. & Agric. Univ.

fYear

2006

fDate

22-24 June 2006

Firstpage

310

Lastpage

315

Abstract

Hardware implementation of the conscience mechanism in Kohonen´s neural networks is presented in this work. The conscience mechanism is an important component of the neural network as it eliminates so called dead neurons leading to larger network efficiency and smaller quantization error. The conscience mechanism itself and winner take all (WTA) block have been implemented in 0.18 mum CMOS process. The design integrated circuit (IC) is a continuation of the earlier effort to produce elements required to implement competitive learning mechanisms in neural networks. The conscience mechanism circuit occupies 270 mum and dissipates maximum power of 22 muW at 2V power supply. The WTA block occupies 0.02 mm and dissipates 50 muW

Keywords

CMOS analogue integrated circuits; integrated circuit design; learning systems; low-power electronics; neural nets; 0.18 micron; 2 V; 22 muW; 270 micron; 50 muW; CMOS analog circuits; Kohonen neural network; WTA block; artificial neural networks; competitive learning mechanisms; conscience mechanism; dead neurons; hardware implementation; integrated circuit design; low power circuits; winner take all block; CMOS process; CMOS technology; Circuits; Learning systems; Neural network hardware; Neural networks; Neurons; Power supplies; Process design; Quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706590

Filename

1706590