Implementation Of The Conscience Mechanism For Kohonen´s Neural Network In Cmos 0.18 /spl mu/m Technology

Hardware implementation of the conscience mechanism in Kohonen´s neural networks is presented in this work. The conscience mechanism is an important component of the neural network as it eliminates so called dead neurons leading to larger network efficiency and smaller quantization error. The conscience mechanism itself and winner take all (WTA) block have been implemented in 0.18 mum CMOS process. The design integrated circuit (IC) is a continuation of the earlier effort to produce elements required to implement competitive learning mechanisms in neural networks. The conscience mechanism circuit occupies 270 mum and dissipates maximum power of 22 muW at 2V power supply. The WTA block occupies 0.02 mm and dissipates 50 muW