Title :
Low-power design of a 64-tap, 4-bit digital matched filter using systolic array architecture and CVSL circuit techniques in CMOS
Author :
Yalcin, Tolga ; Ismailoglu, Neslin
Author_Institution :
Tubitak Bilten VLSI Design Center, Ankara, Turkey
Abstract :
A 4-bit 64-chip pseudo noise (PN) coded digital matched filter (DMF) is designed in 0.7 /spl mu/m CMOS technology using a systolic array (SA) architecture. Full-custom and full-static cascode voltage switch logic (CVSL) circuit techniques have been employed in the implementation of the basic building blocks (systoles) of the SA DMF. Significant reduction in number of transistors and power consumption have been achieved. The resultant IC is to be used at the receiver side of a wireless direct sequence spread spectrum (DSSS) communication system.
Keywords :
CMOS logic circuits; matched filters; median filters; pseudonoise codes; radio receivers; spread spectrum communication; systolic arrays; 0.7 micron; 4 bit; CMOS; CVSL circuit techniques; PN coded filter; direct sequence spread spectrum communication; full-custom integrated circuit; full-static cascode voltage switch logic circuit; low-power design; power consumption reduction; pseudo noise coded digital matched filter; receiver; systolic array architecture; transistors reduction; wireless DS-SS communication system; CMOS logic circuits; CMOS technology; Circuit noise; Logic circuits; Matched filters; Spread spectrum communication; Switches; Switching circuits; Systolic arrays; Voltage;
Conference_Titel :
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5148-7
DOI :
10.1109/ACSSC.1998.751426
