Title :
MPU: a N-tuple matching processor
Author :
Payne, Robert H. ; Delgado-Frias, José G.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
Abstract :
A novel matching processor (MPU) for dataflow architectures is proposed. This processor is capable of matching dataflow nodes requiring n-tuple inputs and reducing dataflow processor load. The main features of this processor include: n-tuple matching, associative matching, maskable match fields, storage reclamation capabilities, maskable ALU operations, and a programmable MPU architecture
Keywords :
parallel architectures; MPU; associative matching; dataflow architectures; dataflow nodes; dataflow processor load; maskable ALU operations; maskable match fields; matching processor; programmable MPU architecture; storage reclamation; Application software; Artificial intelligence; CADCAM; Computational modeling; Computer aided manufacturing; Computer architecture; Concurrent computing; Intelligent robots; Registers; Routing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139886
