Title :
Hardware design of self-organization for clustering
Author :
Ishihara, Atsushi ; Maeda, Yutaka
Author_Institution :
Kansai Univ., Suita
Abstract :
In this paper, we design a self-organization network to classify groups. Using histogram based on outputs of a network, we establish a proper evaluation function defined by the distance between the highest class and the second highest class. Maximizing the evaluation gives proper network. Basic design of this classification network system for FPGA is described. Details of the design are explained. Some simulation results will be shown.
Keywords :
field programmable gate arrays; hardware description languages; logic design; pattern classification; pattern clustering; self-organising feature maps; statistical analysis; FPGA; classification network system; hardware design; histogram; pattern clustering; self-organization network; Design engineering; Education; Electronic mail; Field programmable gate arrays; Histograms; Multi-layer neural network; Neural network hardware; Neural networks; Statistical analysis; Supervised learning; clustering; hardware implementation; neural networks; self-organization;
Conference_Titel :
SICE, 2007 Annual Conference
Conference_Location :
Takamatsu
Print_ISBN :
978-4-907764-27-2
Electronic_ISBN :
978-4-907764-27-2
DOI :
10.1109/SICE.2007.4421136
