Iterative design of frequency synthesizers using CppSim and Matlab

This paper presents a methodology for the system-level design of frequency synthesizers using a combination of programs from the CppSim package and Matlab. These programs allow the user to model the synthesizer considering various design options and to run simulations assisted by a GUI tool. Here, they are included in an optimization loop controlled by an optimization algorithm which assists the user in choosing the design options, from system-level settings - such as the synthesizer type, the loop filter order, the order of the EA modulator, etc. - to block-level parameters - such as the bandwidth of the loop filter. The design of a frequency synthesizer for a direct-conversion DVB-T radio receiver is presented for demonstrating the proposed method.