A Systemc Test Environment For Spin Network

Author

Charlery, H. ; Greiner, A.

Author_Institution

Pierre & Marie Curie Univ., Paris

fYear

2006

fDate

22-24 June 2006

Firstpage

449

Lastpage

453

Abstract

Evaluate system on-chip architectures necessitates test boards and applications. For the comparison between the packet-switched micro-network SPIN and the traditional Pi-Bus we have elaborated SystemC components and multi-threads programs. Instead of using a traffic generator analyzer, component flooding the network with packets, we use a true application running on processor MIPS R3000. By that way we have a various traffic much more realistic. This article describes the way to manage the SystemC simulation and gives details about the structure of an application saturating the Pi-Bus. The results show the importance of an increasing bandwith when we use a parallel application, and also reveal the difficulty we can have to saturate the SPIN network with processors

Keywords

integrated circuit testing; network-on-chip; packet switching; system buses; MIPS R3000; Pi-Bus; SystemC; multithreads programs; network-on-chip; packet switching; scalable programmable integrated network; system-on-chip; test boards; traffic generator analyzer; Bandwidth; Computational modeling; Laboratories; Network-on-a-chip; Protocols; Sockets; System recovery; System testing; System-on-a-chip; Telecommunication traffic;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706620

Filename

1706620