Title :
Processing Time And Cross Capacitive Coupling For A Winner Take All Circuit
Author :
Costea, R.L. ; Marinov, C.A.
Author_Institution :
Bucharest Polytech. Univ.
Abstract :
The paper deals with an analog w(inner)-t(ake)-a(ll) network where two input wires are capacitively coupled. The difference between processing times with and without coupling is evaluated by its upper bound. Thus, a performance criterion explicitly expressed as a function of circuit and processing list parameters is obtained
Keywords :
analogue integrated circuits; capacitance; integrated circuit interconnections; analog winner take all network; cross capacitive coupling; winner take all circuit; Analog circuits; Analog computers; Capacitance; Circuit optimization; Coupling circuits; Integrated circuit interconnections; Signal processing; Steady-state; Upper bound; Wires;
Conference_Titel :
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Conference_Location :
Gdynia
Print_ISBN :
83-922632-2-7
DOI :
10.1109/MIXDES.2006.1706633
