An efficient variable-length tap FIR filter chip

This paper proposes a novel VLSI architecture for an FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a module unit. Since parallel multipliers occupy a large VLSI area, a filter chip using bit-serial multipliers meeting the real-time requirement specification can dramatically save the area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter can be twice faster than previous filters using bit-serial multipliers. We developed VHDL models and performed logic synthesis using the SYNOPSYS^TM CAD tool with the 0.8 μm SOG cell library (HSG30042). The chip has only 9,507 gates, was fabricated, and is running at 77 MHz