A Measurement Technique To Obtain The Delay Time Of A Comparator In 120nm CMOS

The delay time of a regenerative comparator can be in the range of some tens of picoseconds. In this paper, an on-chip measurement technique is presented to obtain this delay time. For this task simple RC low-passes and different variants of implementing a fast XOR gate are examined to determine a short time difference, where after sampling the logic decision at the inverted and non-inverted output of the comparator, both outputs overlap with the same logical value. This time-difference is identified as the delay time of the comparator and occurs, if in the reset phase of the comparator the output nodes are pulled to the same logical value. An advantage of this technique is that only a DC voltage has to be measured outside the chip, which is proportional to the delay time and which is not influenced by bond wire inductances. A test-chip with the low-power comparator and a test-bed for delay-time detection was manufactured in a 120nm CMOS technology with a supply voltage of 1.5V. Compared with simulation results it turns out that a simple RC low-pass is sufficient for delay measurements. When applying a rectangular signal at the input of the implemented comparator, a minimal resolution of 8mV at a clock frequency of 1.5GHz was reached. The power consumption of the comparator was 160muW at 1.5GHz and the offset voltage was typically l0mV