DocumentCode
2639588
Title
Transmission Line Pulsing Tester For On-chip ESD Protection Testing
Author
Piatek, Z. ; Pleskacz, W.A. ; Kolodziejski, J.F.
Author_Institution
Warsaw Univ. of Technol.
fYear
2006
fDate
22-24 June 2006
Firstpage
595
Lastpage
599
Abstract
In the paper transmission line pulsing (TLP) methodology and testers are described. In contrast to commonly available publications, which usually lack information on testers´ design, the authors describe TLP tester´s construction details. This includes an applied electric diagram. Conclusions based on up-to-date research and preliminary test results obtained with the help of the assembled TLP tester are provided
Keywords
electrostatic discharge; integrated circuit testing; system-on-chip; test equipment; transmission lines; ESD protection testing; on-chip; transmission line pulsing tester; Biological system modeling; Circuit testing; Electrostatic discharge; Integrated circuit testing; Power transmission lines; Protection; Pulse measurements; Pulsed power supplies; Transmission lines; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Conference_Location
Gdynia
Print_ISBN
83-922632-2-7
Type
conf
DOI
10.1109/MIXDES.2006.1706650
Filename
1706650
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