Title :
A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor
Author :
Lin, H.-L. ; Lin, H. ; Chang, R.C. ; Chen, S.-W. ; Liao, C.-Y. ; Wu, C.-H.
Author_Institution :
Nat. Chung Hsing Univ.
Abstract :
A high-speed highly pipelined dual-input FFT/IFFT architecture efficiently sharing hardware is proposed for MIMO WLAN communication systems. It reduces the hardware complexity to enhance the throughput of the FFT/IFFT processor to be applied to IEEE 802.11n WLAN system or beyond. The area and the power consumption of the proposed design is 0.66mm2 and 97mW at 200MHz operation frequency with dual input/output 64-point FFT/IFFT sequences using TSMC 0.18mum 1P6M technology at supply voltage of 1.8V
Keywords :
MIMO systems; OFDM modulation; coprocessors; fast Fourier transforms; wireless LAN; 0.18 micron; 1.8 V; 1P6M technology; 200 MHz; 97 mW; FFT/IFFT architecture; IEEE 802.11n WLAN system; MIMO WLAN communication; TSMC; dual OFDM processor; pipelined FFT architecture; Discrete Fourier transforms; Energy consumption; Fast Fourier transforms; Hardware; MIMO; OFDM; Pipelines; Signal processing algorithms; Throughput; Wireless LAN;
Conference_Titel :
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Conference_Location :
Gdynia
Print_ISBN :
83-922632-2-7
DOI :
10.1109/MIXDES.2006.1706659
