Title :
WSI architecture of a neurocomputer module
Author :
Ramacher, Ulrich ; Wesseling, Matthias ; Goser, Karl
Author_Institution :
Siemens AG, Corporate Res. & Dev., Munich, West Germany
Abstract :
Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm2 soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons
Keywords :
CMOS integrated circuits; VLSI; computerised pattern recognition; computerised picture processing; neural nets; parallel processing; 2-dimensional array of multipliers; CMOS; WSI architecture; application; generalized multilayer-perceptrons; implementation; neurocomputer architecture; neurocomputer module; neurocomputing systems; pattern recognition of video images; soft-configured chip; technology related constraints; Artificial neural networks; Computational modeling; Computer architecture; Computer networks; Computer simulation; Concurrent computing; Neural network hardware; Neural networks; Pattern recognition; Semiconductor device modeling;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63892
