Title :
An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm
Author :
Sahin, Esra ; Hamzaoglu, Ilker
Author_Institution :
Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul
Abstract :
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264/MPEG4 part 10 video coding standard. The hardware design is based on a novel organization of the intra prediction equations. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 90 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640times480) per second
Keywords :
field programmable gate arrays; hardware description languages; video coding; FPGA implementation; H.264 intra prediction algorithm; H.264 video coding system; MPEG4 video coding standard; Verilog HDL; Verilog RTL code; hardware architecture; intra prediction equations; Equations; Field programmable gate arrays; Hardware design languages; ISO standards; MPEG 4 Standard; Multiplexing; Prediction algorithms; Standards development; Video coding; Video compression;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
DOI :
10.1109/DATE.2007.364588
