DocumentCode
264056
Title
FPGA implementation of the synchronization for IEEE 802.11n WLAN systems
Author
Minh-Duc Nguyen ; Viet-Tan Nguyen ; Tien-Dat Nguyen ; Xuan-Nghia Nguyen ; Vu-Thang Nguyen ; Vu-Duc Ngo
Author_Institution
Sch. of Electron. & Telecommun., Hanoi Univ. of Sci. & Technol., Hanoi, Vietnam
fYear
2014
fDate
July 30 2014-Aug. 1 2014
Firstpage
280
Lastpage
284
Abstract
Normally, a premable is used for the time synchronization for IEEE 802.11n Wireless LAN (WLAN) systems. However, the synchronization is often affected by the timing of the packet detection and automatic gain control completion (AGC). Therefore, it is invalid to assume that symbol timing synchronization starts at the beginning of the preambles in conventional methods. Moreover, most current timing synchronization methods estimate a coarse time-offset of legacy short training symbols (L-STSs) using complex mathematical expressions such as the cross-correlation or auto-correlation. Implementations of these methods, therefore, are complicated and require a lot of hardware. In order to solve the above problems, an effective symbol timing synchronization method is proposed. The new method can detect the start of frame correctly and can save hardware upto 90.5%, 70.6% and 72.4% compare to conventional and previously proposed methods.
Keywords
correlation methods; field programmable gate arrays; gain control; synchronisation; wireless LAN; AGC; FPGA implementation; IEEE 802.11n; L-STS; WLAN systems; autocorrelation; automatic gain control completion; cross-correlation; legacy short training symbols; packet detection; symbol timing synchronization; wireless LAN systems; Field programmable gate arrays; OFDM; Wireless LAN; FPGA; IEEE 802.11n; Wireless LAN systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Electronics (ICCE), 2014 IEEE Fifth International Conference on
Conference_Location
Danang
Print_ISBN
978-1-4799-5049-2
Type
conf
DOI
10.1109/CCE.2014.6916715
Filename
6916715
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