DocumentCode :
2640576
Title :
Optimized Integration of Test Compression and Sharing for SOC Testing
Author :
Larsson, Anders ; Larsson, Erik ; Eles, Petru ; Peng, Zebo
Author_Institution :
Embedded Syst. Lab., Linkopings Universitet, Linkoping
fYear :
2007
fDate :
16-20 April 2007
Firstpage :
1
Lastpage :
6
Abstract :
The increasing test data volume needed to test core-based system-on-chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a constraint logic programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC ´02 benchmark designs
Keywords :
automatic test equipment; constraint handling; data compression; logic testing; system-on-chip; ATE memory requirements; SOC testing; TAT memory requirement; automatic test equipment memory requirements; constraint logic programming technique; system-on-chip testing; test application times; test architecture design; test data compression; test scheduling; Automatic test equipment; Automatic testing; Circuit testing; Embedded system; Laboratories; Logic programming; Logic testing; System testing; System-on-a-chip; Test data compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
Type :
conf
DOI :
10.1109/DATE.2007.364592
Filename :
4211797
Link To Document :
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