Title :
An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers
Author :
Yoneda, Tomokazu ; Imanishi, Masahiro ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai Science
Abstract :
This paper presents a reconfigurable union wrapper that can wrap multiple cores into a single wrapper design. Moreover, we present a test scheduling algorithm to minimize a test application time using the proposed reconfigurable union wrapper. The proposed heuristic algorithm can achieve short test application time with low computational cost compared to the conventional approaches where every core has its own wrapper. Experimental results for the ITC´02 SOC benchmarks show the effectiveness of our approach
Keywords :
integrated circuit testing; logic testing; reconfigurable architectures; system-on-chip; SoC test scheduling algorithm; heuristic algorithm; reconfigurable union wrappers; system-on-chip; Algorithm design and analysis; Benchmark testing; Computational efficiency; Information science; Logic testing; Processor scheduling; Scheduling algorithm; Switches; System testing; System-on-a-chip; reconfigurable union wrapper; system-on-a-chip; test access mechanism; test scheduling;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
DOI :
10.1109/DATE.2007.364596