Hardware modelling of frequency recovery in an upstream demodulator for DOCSIS 3.0

For many communication systems, frequency offset is inevitable, since even minute differences between different oscillators are typically sufficient to cause this problem. The challenge is exacerbated by other non-ideal effects, including intersymbol interference (ISI). In this paper, the hardware modelling issues are considered for a frequency recovery scheme that has been previously shown to approach the Cramer-Rao Lower Bound (CRLB) and is immune to ISI-induced biasing. The associated design and implementation are pursued in the context of a DOCSIS 3.0 upstream demodulator. To investigate the correspondences, with issues and implications, between theoretical and practical hardware-level performances, the frequency recovery scheme is implemented in MATLAB and Altera DSP Builder, which offers hardware-oriented modelling. The obtained results and analysis, which are performed by comparing corresponding outputs from MATLAB and Altera DSP Builder, show good match and support the practical validity of the frequency recovery scheme for DOCSIS 3.0.