A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

Author

Oude Alink, M.S. ; Klumperink, E.A.M. ; Kokkeler, A.B.J. ; Wei Cheng ; Zhiyu Ru ; Ghaffari, A. ; Wienk, G.J.M. ; Nauta, B.

Author_Institution

Integrated Circuit Design/Comput. Archit. for Embedded Syst., Univ. of Twente, Enschede, Netherlands

fYear

2012

fDate

17-19 June 2012

Firstpage

35

Lastpage

38

Abstract

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3-1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP₃, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth.

Keywords

CMOS integrated circuits; cognitive radio; radio receivers; spectral analysers; CMOS spectrum analyzer frontend; RF input-signal attenuation; bandwidth 1 MHz; cognitive radio; digital baseband; discrete-step attenuators; dual-RF receiver; frequency 0.3 GHz to 1.0 GHz; receiver noise; resolution bandwidth; size 65 nm; spurious-free dynamic range; Attenuation; Attenuators; CMOS integrated circuits; Linearity; Noise; Noise measurement; Receivers; IIP3; cognitive radio; cross-correlation; energy detection; linearity; noise figure; spectrum analyzer; spectrum sensing; spurious-free dynamic range;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Conference_Location

Montreal, QC

ISSN

1529-2517

Print_ISBN

978-1-4673-0413-9

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2012.6242226

Filename

6242226