DocumentCode :
2641066
Title :
Timing in systolic systems with variable minimum connection delays
Author :
Ott, Maximilian ; Enami, Kazumasa ; Hatori, Mitsutoshi ; Aizawa, Kiyoharu
Author_Institution :
Dept. of Electr. Eng., Tokyo Univ., Japan
fYear :
1990
fDate :
1-3 May 1990
Firstpage :
2248
Abstract :
Mapping an originally delay-free dataflow graph onto a systolic hardware consisting of various programmable ALUs (arithmetic logic unit) and a programmable network connecting them will introduce variable extra delays between the processing nodes. To ensure successful mapping it will usually be necessary to increase some of the delays. An algorithm is introduced for calculating these delays and the position to add them. This algorithm was implemented in PicPEn, a programming environment created for the Picot system
Keywords :
delays; graph theory; logic CAD; systolic arrays; CAD; PicPEn; Picot system; arithmetic logic unit; computer aided design; delay-free dataflow graph; mapping; programmable ALUs; programmable network; programming environment; systolic systems; variable minimum connection delays; Clocks; Delay; Digital signal processing; Equations; Hardware; Joining processes; Laboratories; Pipeline processing; Throughput; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
Type :
conf
DOI :
10.1109/ISCAS.1990.112341
Filename :
112341
Link To Document :
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