A unique approach to built-in-self-test circuit design

Author

Al-Arian, Sami A. ; Abujbara, Hussam Y. ; Ruel, Jim C.

Author_Institution

Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

270

Lastpage

274

Abstract

A partitioning scheme and a self-test architecture for a wafer scale integration (WSI) FFT multiply-subtract-add (MSA) cell is described. The partitioning scheme, is used to reduce the number of the test vectors needed to cover all faults. The built-in self-test (BIST) technique incorporated into the design is described and is based on a deterministic test vector generation and sequence detector. The fault coverage of the processor was evaluated at over 99%. The fault models considered included stuck-at and bridging faults. The total increase in the area overhead at the cell level was evaluated to be less than 15%. This increase is justified on the grounds that the cells are now easily testable. The BIST circuitry is implemented in each processing element (PE) and is designed to test both the PE and the entire WSI system. The BIST approach can considerably reduce the test and probing time for evaluating test vectors via automatic test equipment

Keywords

VLSI; built-in self test; fault location; FFT multiply-subtract-add; automatic test equipment; bridging faults; built-in-self-test circuit design; deterministic test vector generation; fault models; partitioning scheme; self-test architecture; sequence detector; stuck-at; test vectors; wafer scale integration; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Computer architecture; Computer science; Costs; Microelectronics; System testing; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139896

Filename

139896