A 34% PAE, 18.6dBm 42–45GHz stacked power amplifier in 45nm SOI CMOS

Author

Agah, Amir ; Dabag, Hayg ; Hanafi, Bassel ; Asbeck, Peter ; Larson, Lawrence ; Buckwalter, James

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, La Jolla, CA, USA

fYear

2012

fDate

17-19 June 2012

Firstpage

57

Lastpage

60

Abstract

A two-stack 42-45GHz power amplifier is implemented in 45nm SOI CMOS. Transistor stacking allows increased drain biasing to increase output power. Additionally, shunt inter-stage matching is used and improves PAE by more than 6%. This amplifier exhibits 18.6dBm saturated output power, with peak power gain of 9.5dB. It occupies 0.3mm² including pads while achieving a peak PAE of 34%. The PAE remains above 30% from 42 to 45GHz.

Keywords

CMOS analogue integrated circuits; millimetre wave integrated circuits; millimetre wave power amplifiers; silicon-on-insulator; SOI CMOS; drain biasing; efficiency 34 percent; frequency 42 GHz to 45 GHz; gain 9.5 dB; shunt interstage matching; size 45 nm; transistor stacking; two-stack power amplifier; CMOS integrated circuits; CMOS technology; FETs; Gain; Power amplifiers; Power generation; Semiconductor device measurement; CMOS SOI; Power amplifier; inter-stage matching; millimeter-wave; slow-wave CPW; stacked;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Conference_Location

Montreal, QC

ISSN

1529-2517

Print_ISBN

978-1-4673-0413-9

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2012.6242231

Filename

6242231