DocumentCode
2641202
Title
An improved least squares solution technique for multi-processor architecture
Author
Dhar, Kaushal K.
Author_Institution
Inst. for Commun. Technol., Swiss Federal Res. Inst., Zurich, Switzerland
fYear
1990
fDate
1-3 May 1990
Firstpage
1199
Abstract
An approach is suggested to map the solution of the least-square (LS) problem, using Gram-Schmidt (GS) orthogonalization, on a distributed memory parallel processing (DMPP) architecture. Using algorithmic partitioning, the resulting lower-order problems are mapped concurrently on the architecture concerned so that the computational loads are more evenly balanced than when the conventional method is applied. This results in much higher multiprocessor efficiencies. Specific implementation advantages are seen to exist for the partitioning factors which are a power of 2. DMPP architectures are very useful for future implementation of high speed digital processing (DSP) applications because of the excellent potential they offer for being able to be implemented in the form of VLSIs. The solution of the problem concerned on the ring and torus topologies is discussed
Keywords
VLSI; computerised signal processing; least squares approximations; parallel architectures; DMPP; Gram-Schmidt orthogonalization; VLSIs; algorithmic partitioning; computational loads; distributed memory parallel processing; high speed digital processing; least squares solution technique; lower-order problems; multi-processor architecture; multiprocessor efficiencies; partitioning factors; ring topologies; torus topologies; Communications technology; Computer architecture; Digital signal processing; Equations; Geophysics computing; Iterative algorithms; Least squares methods; Signal processing algorithms; Spectral analysis; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112342
Filename
112342
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