Title :
Low-Power Double Edge-Triggered Flip-Flop Circuit Design
Author_Institution :
Dept. of Electron. Eng., Hsiuping Inst. of Technol., Taichung
Abstract :
In this paper, we compare three previously published static double edge-triggered (DET) flip-flops with a proposed design for their transistor counts and power consumptions. The proposed DET flip-flop uses only 12 transistors in addition to the clock driver, and hence requires a small area. Several HSPICE simulations with different input sequences show that the proposed DET flip-flop reduces power consumption up to 85%, as compared to conventional DET flip-flops.
Keywords :
SPICE; flip-flops; integrated circuit design; logic design; low-power electronics; HSPICE simulation; clock driver; low-power double edge-triggered flip-flop circuit design; power consumption; transistor; CMOS technology; Circuit synthesis; Clocks; Energy consumption; Flip-flops; Frequency; Latches; Master-slave; Power engineering and energy; Very large scale integration;
Conference_Titel :
Innovative Computing Information and Control, 2008. ICICIC '08. 3rd International Conference on
Conference_Location :
Dalian, Liaoning
Print_ISBN :
978-0-7695-3161-8
Electronic_ISBN :
978-0-7695-3161-8
DOI :
10.1109/ICICIC.2008.342
