Title :
A 2.74–5.37GHz boosted-gain type-I PLL with <15% loop filter area
Author :
Sun, Yuanfeng ; Li, Jun ; Zhang, Zhuo ; Wang, Min ; Xu, Ni ; Lv, Hang ; Rhee, Woogeun ; Li, Yongming ; Wang, Zhihua
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
This paper describes a 64% locking-range type-I LC PLL architecture with a small loop filter area. By employing a dual-path LC VCO with a boosted open-loop gain at dc, a reference spur or a static phase error problem with a large frequency offset in the type-I PLL is alleviated. The prototype PLL is implemented in 0.13μm CMOS, achieving 2.74-to-5.37GHz locking range with <;-50dBc reference spur over active locking range.
Keywords :
CMOS integrated circuits; LC circuits; MMIC oscillators; UHF filters; UHF oscillators; microwave filters; phase locked loops; voltage-controlled oscillators; CMOS implementation; boosted open loop gain; boosted-gain type-I PLL; dual-path LC VCO; frequency 2.74 GHz to 5.37 GHz; frequency offset; locking-range type-I LC PLL architecture; loop filter area; reference spur; static phase error problem; CMOS integrated circuits; Capacitors; Filtering theory; Phase locked loops; Tuning; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0413-9
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2012.6242259
