Concurrent L- and S-band class-E power amplifier in 65nm CMOS

Author

Zhang, Ronghui ; Acar, Mustafa ; Apostolidou, Melina ; Van der Heijden, Mark P. ; Leenaerts, Domine M W

Author_Institution

NXP Semicond., Eindhoven, Netherlands

fYear

2012

fDate

17-19 June 2012

Firstpage

217

Lastpage

220

Abstract

A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (η) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power P_out >; 30.4dBm. For S-band (2.8-3.1GHz) a η >; 42.6% and a PAE >; 30% with a P_out >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.

Keywords

CMOS analogue integrated circuits; UHF power amplifiers; nanoelectronics; CMOS; CMOS concurrent dual-band two-stage class-E power amplifier; L-band class-E power amplifier; S-band class-E power amplifier; class-E load impedance; concurrent transmission-line based dual-band output matching network; drain efficiency; frequency 1 GHz to 3.1 GHz; high voltage extended-drain device; power-added efficiency; size 65 nm; CMOS integrated circuits; Dual band; Impedance; Impedance matching; L-band; Power generation; Switches; CMOS power amplifier; Class-E; Dual-band;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Conference_Location

Montreal, QC

ISSN

1529-2517

Print_ISBN

978-1-4673-0413-9

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2012.6242267

Filename

6242267