Title :
Fault detection in VLSI circuits
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., MN, USA
Abstract :
In this paper, an algorithm for fault detection in VLSI circuits is presented. This algorithm is based on partitioning combinational and sequential circuits for pseudo-exhaustive testing. The partitioning algorithm is based on an analysis of a circuit´s primary input cones and fanout values. Once a circuit has been partitioned, its primary outputs and partitioned points are tested exhaustively. By exhaustively testing individual blocks, faults within these blocks are detected and located. The results show that the partitioning algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms. In addition, the algorithm is based upon pseudo-exhaustive testing methods where fault simulation is not required for test pattern generation and grading; hence, engineering design time and cost are further reduced.
Keywords :
VLSI; combinational circuits; failure analysis; fault location; integrated circuit reliability; integrated circuit testing; logic partitioning; logic testing; sequential circuits; VLSI circuits; combinational circuit partitioning; engineering design cost; engineering design time; fanout values; fault detection; fault detection algorithm; fault location; fault simulation; partitioned points; partitioning algorithm; primary input cones; pseudo-exhaustive testing; pseudo-exhaustive testing methods; sequential circuit partitioning; test overhead reduction; test pattern generation; test time; Algorithm design and analysis; Circuit analysis; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Partitioning algorithms; Sequential analysis; Sequential circuits; Very large scale integration;
Conference_Titel :
Microelectronics, 1999. ICM '99. The Eleventh International Conference on
Print_ISBN :
0-7803-6643-3
DOI :
10.1109/ICM.2000.884815
